1. Field of the Invention
This invention relates to a semiconductor device, and more specifically to a bipolar transistor.
2. Description of the Prior Art
Referring to FIG. 1, there is illustrated a sectional view of a prior art NPN bipolar transistor which includes a base formed through ion implantation and which employs a self-alignment process, the bipolar transistor including a p.sup.- type silicon substrate 201, an n.sup.+ type buried layer, an n.sup.- type silicon epitaxial layer 203 formed on the former layer 202, and a LOCOS oxide film 204. The n.sup.+ type buried layer 202 is connected to an A1 electrode 216 through an n.sup.+ type phosphorus diffusion layer 205 and an n.sup.+ type collector electrode polycrystalline silicon 208. A p.sup.+ type intrinsic base 217 formed through ion implantation on the surface of the n.sup.- type silicon epitaxial layer 203 is connected with the side surface of a p.sup.+ type external base 218 formed on the surface of the n.sup.- type silicon epitaxial layer 203 through impurity diffusion from a p.sup.+ type base electrode polycrystalline silicon 207. Further, an n.sup.+ type emitter 220 is formed on the surface of the intrinsic base 217 through impurity diffusion from n.sup.+ type emitter electrode polycrystalline silicon 219. Silicon oxide films 206, 214, and a silicon nitride film 209 electrically insulates the respective portions mentioned above. The above construction is basically the same as an SST (Super Self-Aligned Process Technology) one reported in the Proceedings of the 12th Solid State Devices Conference: Proc. of Solid State Device, P155, 1980.
The aforementioned prior art bipolar transistor is configured into a structure suitable for the formation of a base through an ion implantation process. Such an ion implantation process however suffers from a difficulty with channeling, and hence has in itself a limitation to a technique where a base is formed as a thin film. Further, as implantation conditions go to lower implantation energy and to higher doses for the purpose of a base making thinner, a heat teatment at a temperature lower than a predetermined one and within a predetermined period of time makes impossible the recovery of implantation damage and the activation of impurities.
Additionally, the foregoing bipolar transistor has another difficulty caused by its fabrication method. More specifically, the formation of a base of the foregoing bipolar transistor includes the following processes. A base electrode polycrystalline silicon is patterned, on the side wall of which is polycrystalline silicon an insulating film is formed, and an insulating film provided under which polycrystalline film is side-etched, and thereafter a non-implanted polycrystalline silicon is deposited by an LPCVD process, into which non-implanted polycrystalline silicon impurity is in turn diffused from an overhung portion of the foregoing base electrode polycrystalline silicon through a heat treatment. The non-implanted polycrystalline silicon is kept non-implanted as before excepting the lower part of the overhung portion. When the additional part of the polycrystalline silicon kept non-implanted is wet-etched by hydrazine and KOH, etc., and use is made of a (100)-oriented single crystal silicon substrate, etching rates of the single crystal silicon and the non-implanted polycrystalline silicon being wet-etched, the etching is advancd up to the (100)-oriented intrinsic base. This impedes in the prior art bipolar transistor the use of the (100)-oriented single crystal silicon substrate.
In contrast, there is disclosed a bipolar transistor with use of a low temperature epitaxial technique promising as the thin film base formation technique in the proceedings of the VLSI Technology Symposium (Symp. on VLSI Technology, pp. 91-92, 1989). More specifically, a base electrode polycrystalline silicon is patterned on a collector, and thereafter an epitaxial layer is grown to form a single crystal on a region where the aforementioned base electrode polycrystalline silicon is absent Since in this structure the emitter and the base fail to be formed in a self-alignment manner, an emitter opening part is needed to be formed on the single crystal base through lithography. This essentially results in a limitation to reduction of the device and makes it impossible to really produce parasitic capacitance and parasitic resistance. It is therefore impossible to realize a high speed bipolar transistor using the above structure.
There is further disclosed a technique to suppress Kirk effect by implanting phosphorus ion into a collector disposed just under an emitter for the purpose of achieving a high f.sub.T in the proceedings of the 19th Solid State Device and Materials Conference (Proceedings of Solid State Devices and Materials, pp.331-334, 1987). The technique surely enjoys a higher cut-off frequency f.sub.T, but causes the severe deterioration of junction breakdown voltage because the junction is formed between a high concentration base and a high concentration collector. For improving such breakdown voltage a p-i-n structure may be constructed to prevent a direct junction from being formed between the high concentration base and the high concentration collector by disposing an i layer between those base and collector. Upon constructing such a structure through an ion implantation process a uniform concentration thicker i layer fails to be formed because of the affection of the tail of an impurity Gaussian distribution yielded upon ion implantation. For improving the breakdown voltage by moderating an electric field in a depletion layer between the collector and the base, an i layer with the width of the same order (i.e., about 100 nm) as that of the depletion layer, which is impossible in view of the aforementioned reason.